View FIN3386MTDX_5743253.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

march 2012 ? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 fin3385 / fin3386 ? low- v olta g e , 28-bit flat panel dis p la y link serializer / deserializer fin3385 / fin3386 low-voltage, 28-bit, flat-panel display link serializer / deserializer features ? operation -40c to +85c ? low power consumption ? 20mhz to 85mhz shift clock support ? 1v common-mode range around 1.2v ? narrow bus reduces cable size and cost ? high throughput (up to 2.38gbps) ? internal pll with no external component ? compatible with tia/ eia-644 specification ? 56-lead, tssop package description the fin3385 and fin3386 transform 28-bit wide parallel low-voltage ttl (lvttl) data into four serial low voltage differential signaling (lvds) data streams. a phase-locked transmit clock is transmitted in parallel with the data stream over a separate lvds link. every cycle of transmit clock, 28-bi ts of input lvttl data are sampled and transmitted. the fin3386 receives and conver ts the 4/3 serial lvds data streams back into 28/21 bi ts of lvttl data, acting as the deserializer. for the fin3385, at a transmit clock frequency of 85mhz, 28-bits of lvttl data are transmitted at a rate of 595mbps per lvds channel. this pair solves emi and cable size problems associated with wide and high-speed ttl interfaces. ordering information part number operating temperature range package packing method fin3385mtdx -40 to +85c 56-lead thin-shrink small-outline package (tssop), jedec mo-153,6.1mm wide tape and reel FIN3386MTDX
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 2 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer block diagrams figure 1. fin3385 transm itter functional diagram figure 2. fin3386 receiver functional diagram
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 3 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer transmitter pin configuration figure 3. fin3385 (28:4 tran smitter) pin assignments pin definitions pin names i/o types number of pins description of signals txin i 28/21 lvttl level input txclkin i 1 lvttl level clock inpu t, the rising edge is for data strobe txout+ o 4/3 positive lvds differential data output txout- o 4/3 negative lvds differential data output txclkout+ o 1 positive lvds differential clock output txclkout- o 1 negative lvds differential clock output r_fb i 1 rising edge data strobe: assert high (v cc ) falling edge data strobe: assert low (ground) /pwrdn i 1 lvttl level power-down input assertion (low) puts the outputs in high-impedance state pll v cc i 1 power supply pin for pll pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pin for lvds output lvds gnd i 3 ground pins for lvds output v cc i 3 power supply pins for lvttl input gnd i 5 ground pin for lvttl input
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 4 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer receiver pin configuration figure 4. fin3386 (28:4 r eceiver) pin assignments pin definitions pin names i/o types number of pins description of signals rxin i 4/3 negative lvds differential data output rxin+ i 4/3 positive lvds differential data output rxclkin- i 1 negative lvds differential data input rxclkin+ i 1 positive lvds differential clock input rxout o 28/21 lvttl level data ou tput, goes high for /pwrdn low rxclkout- o 1 lvttl clock output /pwrdn i 1 lvttl level input. refer to table 2 pll v cc i 1 power supply pin for pll pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pin for lvds input lvds gnd i 3 ground pins for lvds input v cc i 4 power supply for lvttl output gnd i 5 ground pins for lvttl output
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 5 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer truth tables table 1. input / output truth table inputs outputs txin txclkin /pwrdn (1) txout txclkout active active high lo w / high low / high active low / high / high impedanc e high low / high don?t care (2) floating active high low low / high floating floating high low don?t care (2) don?t care don?t care low high impedance high impedance notes: 1. the outputs of the transmitter or receiv er remain in a high-impedance state until v cc reaches 2v. 2. txclkout settles at a free-r unning frequency when the part is powered up, /pwrdn is high, and the txclkin is a steady logic level (low / high / high-impedance). power-up / power-down operation truth tables the outputs of the transmitter remain in the high-impedance state until the power supply reaches 2v. table 2 shows the operation of the transmitter during power-up and power-down and oper ation of the /pwrdn pin. table 2. transmitter power-up / power-down operation truth table pwrdn normal v cc <2v >2v >2v txin don?t care don?t care active txout high impedance high impedance active txclkin don?t care don?t care active txclkout high impedance high impedance active /pwrdn low low high table 3. receiver power-up / power-down operation truth table /pwrdn rxin don?t care don?t care ac tive active note 3 note 3 rxout high impedance low low/high last valid state high last valid state rxclkin don?t care don?t care active note 3 note 3 note 3 rxclkout high impedance note 4 active note 4 note 4 note 4 /pwrdn low low high high high high v cc <2v <2v <2v <2v <2v <2v notes: 3. if the input is terminated and un- driven (high-impedance) or short ed or open (fail-safe condition). 4. for /pwrdn or fail-safe condition, the rxclkout pin goes low for panel link devices and high for channel link devices. 5. shorted means ( inputs are shor ted to each other, or inputs are shorted to each other and ground or v cc , or either inputs are shorted to ground or v cc ) with no other current/voltage sources (noise) applied. if the v id is still in the valid range (greater than 100mv) and v cm is in the valid range (0v to 2.4v), the input signal is still recognized and the part responds normally.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 6 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc power supply voltage -0.3 +4.6 v v id_ttl ttl/cmos input/output voltage -0.5 +4.6 v v io_lvds lvds input/output voltage -0.3 +4.6 v i osd lvds output short-circu it current continuous t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature, solderi ng, 4 seconds +260 c esd human body model, jesd22-a114 (1.5k ? ,100pf) i/o to gnd >10.0 kv all pins >6.5 machine model, jesd22-a115 (0 ? , 200pf) >400 v note: 6. absolute maximum ratings are dc values beyond wh ich the device may be damaged or have its useful life impaired. the datasheet specif ications should be met, without exception, to ensure that the system design is reliable over its power supply, temper ature, and output/input loading variables. recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a operating temper ature -40 +85 c v ccnpp maximum supply noise voltage (7) 100 mv pp note: 7. 100mv v cc noise should be tested for frequency at least up to 2mhz. all the specificat ions should be met under such noise.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 7 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer transmitter dc electrical characteristics typical values are at t a =25c and with v cc =3.3v; minimum and maximum are at over supply voltages and operating temperatures ranges, unle ss otherwise specified. symbol parameter condition min. typ. max. unit transmitter lvttl input characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v ik input clamp voltage i ik =-18ma -0.79 -1.50 v i in input current v in =0.4v to 4.6v 1.8 10.0 a v in =gnd -10 0 transmitter lvds output characteristics (8) v od output differential voltage r l =100 ? , figure 5 250 450 mv ? v od v od magnitude change from differential low-to-high 35 mv v os offset voltage 1.125 1.250 1.375 v ? v os offset magnitude change from differential low-to-high 25 mv i os short-circuit output current v out =0v -3.5 -5.0 ma i oz disabled output leakage current do=0v to 4.6v, /pwrdn=0v 1 10 a transmitter supply current i ccwt 28:4 transmitter power supply current for worst-case pattern (with load) (9) r l =100 ? figure 8 32.5mhz 31.0 49.5 ma 40mhz 32.0 55.0 66mhz 37.0 60.5 85mhz 42.0 66.0 i ccpdt powered-down supply current /pwrdn=0.8v 10.0 55.0 a i ccgt 28:4 transmitter supply current for 16 grayscale (9) figure 23 (10) 32.5mhz 29.0 41.8 ma 40mhz 30.0 44.0 66mhz 35.0 49.5 85mhz 39.0 55.0 notes: 8. positive current values re fer to the current flowing into device and negativ e values refer to current flowing out of pins. voltages are referenced to ground unless otherwise specified (except ? v od and v od ). 9. the power supply current for both transmitter and receiv er can vary with the number of active i/o channels. 10. the 16-grayscale test pattern tests device power cons umption for a ?typical? lcd display pattern. the test pattern approximates signal switching needed to produce gr oups of 16 vertical strips across the display.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 8 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer transmitter ac electrical characteristics typical values are at t a =25c and with v cc =3.3v; minimum and maximum are at over supply voltages and operating temperatures ranges, unle ss otherwise specified. symbol parameter condition min. typ. max. unit t tcp transmit clock period figure 9 11.76 t 50.00 ns t tch transmit clock (txclkin) high time 0.35 0.50 0.65 t t tcl transmit clock low time 0.35 0.50 0.65 t t clkt txclkin transition time (rising and falling) (10% to 90%) figure 10 1.0 6.0 ns t jit txclkin cycle-to-cycle jitter 3.0 t xit txin transition time 1.5 6.0 ns lvds transmitter timing characteristics t tlh differential output rise time (20% to 80%) figure 8 0.75 1.50 ns t thl differential output fall time (20% to 80%) 0.75 1.50 ns t stc txin setup to txclnin figure 9 f=85mhz 2.5 ns t htc txin holds to txclnin 0 ns t tpdd transmitter power-down delay figure 14 (11) 100 ns t tccd transmitter clock input to clock output delay (t a =25c and with v cc =3.3v) figure 13 2.8 5.5 6.8 ns transmitter output data jitter (f=40mhz) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a ? ? -0.25 0 0.25 ns t tppb1 transmitter output pulse positi on of bit 1 a-0.25 a a+0.25 ns t tppb2 transmitter output pulse positi on of bit 2 2a-0.25 2a 2a+0.25 ns t tppb3 transmitter output pulse positi on of bit 3 3a-0.25 3a 3a+0.25 ns t tppb4 transmitter output pulse positi on of bit 4 4a-0.25 4a 4a+0.25 ns t tppb5 transmitter output pulse positi on of bit 5 5a-0.25 5a 5a+0.25 ns t tppb6 transmitter output pulse positi on of bit 6 6a-0.25 6a 6a+0.25 ns transmitter output data jitter (f=65mhz) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a ? ? -0.2 0 0.2 ns t tppb1 transmitter output pulse positi on of bit 1 a-0.2 a a+0.2 ns t tppb2 transmitter output pulse positi on of bit 2 2a-0.2 2a 2a+0.2 ns t tppb3 transmitter output pulse positi on of bit 3 3a-0.2 3a 3a+0.2 ns t tppb4 transmitter output pulse positi on of bit 4 4a-0.2 4a 4a+0.2 ns t tppb5 transmitter output pulse positi on of bit 5 5a-0.2 5a 5a+0.2 ns t tppb6 transmitter output pulse positi on of bit 6 6a-0.2 6a 6a+0.2 ns continued on the following page?
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 9 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer transmitter ac electrical characteristics (continued) over supply voltage and operati ng temperature ranges, unle ss otherwise specified. symbol parameter condition min. typ. max. unit transmitter output data jitter (f=85mhz) (12) t tppb0 transmitter output pulse position of bit 0 figure 20 7 f 1 a ? ? -0.2 0 0.2 ns t tppb1 transmitter output pulse positi on of bit 1 a-0.2 a a+0.2 ns t tppb2 transmitter output pulse positi on of bit 2 2a-0.2 2a 2a+0.2 ns t tppb3 transmitter output pulse positi on of bit 3 3a-0.2 3a 3a+0.2 ns t tppb4 transmitter output pulse positi on of bit 4 4a-0.2 4a 4a+0.2 ns t tppb5 transmitter output pulse positi on of bit 5 5a-0.2 5a 5a+0.2 ns t tppb6 transmitter output pulse positi on of bit 6 6a-0.2 6a 6a+0.2 ns t jcc fin3385 transmitter clock out jitter, cycle-to-cycle, figure 20 f=40mhz 350 370 ps f=65mhz 210 230 f=85mhz 110 150 t tplls transmitter phase lock loop set time (13) figure 26 (12) 10 ms notes : 11. outputs of all transmitters stay in 3-state until power reaches 2v. clock and data output begins to toggle 10ms after v cc reaches 3.0v and /pwrdn pin is above 1.5v. 12. this output data pulse position wor ks for both transmitters for ttl inputs, except the lvds output bit mapping difference (see figure 18) . figure 20 shows the skew between the first data bit and clock output. a two-bit cycle delay is guaranteed when the msb is output from transmitter. 13. this jitter specification is based on the assumption that pll has a reference clock with cycle-to-cycle input jitter of less than 2ns.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 10 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer receiver dc characteristics typical values are at t a =25c and with v cc =3.3v. minimum and maximum values are over supply voltage and operating temperature ranges unle ss otherwise specified. positive current va lues refer to the current flowing into device and negative values refer to current flowing out of pins. voltages are referenced to ground unless otherwise specified (except ? v od and v od ). symbol parameter condition min. typ. max. unit lvttl/cmos dc characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v oh output high voltage i oh =-0.4ma 2.7 3.3 v v ol output low voltage i ol =2ma 0.06 0.30 v v ik input clamp voltage i ik =-18ma -0.79 -1.50 v i in input current v in =0v to 4.6v -10 10 ? a i off input/output power-off leakage current v cc =0v, all lvttl inputs / outputs 0v to 4.6v 10 ? a i os output short-circuit current v out =0v -60 -120 m ? receiver lvds input characteristics v th differential input threshold high figure 6, table 4 100 mv v tl differential input threshold low figure 6, table 4 -100 mv v icm input common mode range figur e 6, table 4 0.05 2.35 v i in input current v in =2.4v, v cc =3.6v or 0v 10 ? a v in =0v, v cc =3.6v or 0v 10 receiver supply current i ccwr 4:28 receiver power supply current for worst-case pattern with load (14) c l =8pf, figure 7 32.5mhz 70 ma 40.0mhz 75 3:21 receiver power supply current for worst-case pattern with load (14) 66.0mhz 114 85.0mhz 135 32.5mhz 49 60 40.0mhz 53 65 66.0mhz 78 100 85.0mhz 90 115 i ccpdt powered-down supply current /pwrdn =0.8v (rxout stays low) na 55 ? a
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 11 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer receiver ac characteristics typical values are at t a =25c and with v cc =3.3v; minimum and maximum are at over supply voltages and operating temperatures ranges, unle ss otherwise specified. symbol parameter condition min. typ. max. unit t rcop receiver clock output (rxclkout) period figure 12 rising edge strobe f=85mhz 11.76 t 50.00 t rcol rxclkout low time 4.0 5.0 6.0 ns t rcoh rxclkout high time 4.5 5.0 6.5 ns t rsrc rxout valid prior to rxclkout 3.5 ns t rhrc rxout valid after rx clkout 3.5 ns t rolh output rise time (20% to 80%) c l =8pf, figure 8 2.0 3.5 ns t rohl output fall time (80% to 20%) 1.8 3.5 t rccd receiver clock input to clock output delay (15) t a =25c, v cc =3.3v, figure 24 3.5 5.0 7.5 ns t rppd receiver power-down delay figure 17 1.0 s t rspb0 receiver input strobe position of bit 0 figure 21 f=85mhz 0.49 0.84 1.19 ns t rspb1 receiver input strobe positi on of bit 1 2.17 2.52 2.87 ns t rspb2 receiver input strobe positi on of bit 2 3.85 4.20 4.55 ns t rspb3 receiver input strobe positi on of bit 3 5.53 5.88 6.23 ns t rspb4 receiver input strobe positi on of bit 4 7.21 7.56 7.91 ns t rspb5 receiver input strobe positi on of bit 5 8.89 9.24 9.59 ns t rspb6 receiver input strobe positi on of bit 6 10.57 10.92 11.27 ns t rskm rxin skew margin (16) figure 21 290 ps t rplls receiver phase lock loop set time figure 21 10 ms t rcop receiver clock output (rxclkout) period figure 12 15 t 50 ns t rcol rxclkout low time figure 12 rising edge strobe f=40mhz 10.0 11.0 ns t rcoh rxclkout high time 10.0 12.2 t rsrc rxout valid prior to rxclkout 6.5 11.6 t rhrc rxout valid after rxclkout 6.0 11.6 t rcol rxclkout low time figure 12, rising edge strobe (17) f=66mhz 5.0 6.3 9.0 ns t rcoh rxclkout high time 5.0 7.6 9.0 t rsrc rxout valid prior to rxclkout 4.5 7.3 t rhrc rxout valid after rxclkout 4.0 6.3 t rolh output rise time (20% to 80%) c l =8pf (17) , figure 12 2.0 5.0 ns t rohl output fall time (20% to 80%) 1.8 5.0 t rccd receiver clock input to clock output delay (18) figure 14, t a =25c and v cc =3.3v 3.5 5.0 7.5 ns t rpdd receiver power-down delay figure 17 1.0 s t rspb0 receiver input strobe position of bit 0 figure 21, f=40mhz 1.00 1.40 2.15 ns t rspb1 receiver input strobe posi tion of bit 1 4.50 5.00 5.80 t rspb2 receiver input strobe posi tion of bit 2 8.10 8.50 9.15 t rspb3 receiver input strobe posi tion of bit 3 11.6 11.9 12.6 t rspb4 receiver input strobe posi tion of bit 4 15.1 15.6 16.3 t rspb5 receiver input strobe posi tion of bit 5 18.8 19.2 19.9 t rspb6 receiver input strobe posi tion of bit 6 22.5 22.9 23.6
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 12 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer receiver ac characteristics typical values are at t a =25c and with v cc =3.3v; minimum and maximum are at over supply voltages and operating temperatures ranges, unle ss otherwise specified. symbol parameter condition min. typ. max. unit t rspb0 receiver input strobe position of bit 0 figure 21, f=66mhz 0.7 1.1 1.4 ns t rspb1 receiver input strobe posi tion of bit 1 2.9 3.3 3.6 t rspb2 receiver input strobe posi tion of bit 2 5.1 5.5 5.8 t rspb3 receiver input strobe posi tion of bit 3 7.3 7.7 8.0 t rspb4 receiver input strobe posi tion of bit 4 9.5 9.9 10.2 t rspb5 receiver input strobe posi tion of bit 5 11.7 12.1 12.4 t rspb6 receiver input strobe posi tion of bit 6 13.9 14.3 14.6 t rskm rxin skew margin (19) f=40mhz, figure 21 490 ps f=66mhz, figure 21 400 t rplls receiver phase lock loop set time figure 15 10.0 ms notes: 14. the power supply current for the receiver can vary with the number of i/o channels. 15. total channel latency from seria lizer to deserializer is (t + t tccd ) where t is a clock period. 16. receiver skew margin is defined as the valid samp ling window after considering potential setup/hold time and minimum/maximum bit position. 17. for the receiver with falling-edge str obe, the definition of setup/hold time is slightly different from the one with rising-edge strobe. the clock reference point is the time when the clock falling edge passes through 2v. for hold time t rhrc , the clock reference point is the time when falling edge passes through +0.8v. 18. total channel latency from seria lizer to deserializer is (t + t ccd ) (2?t + t rccd ) where t is the clock period. 19. receiver skew margin is defined as the valid samp ling window after considering potential setup/hold time and minimum / maximum bit position.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 13 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer test circuits figure 5. differential lvds output dc test circuit notes : a: for all input pulses, t r or t f <=1ns. b: c l includes all probe and jig capacitance. figure 6. differential receiver voltage definitions, pr opagation delay, and transition time test circuit table 4. receiver minimum and maximum input threshold test voltages applied voltages (v) resulting differential input voltage (mv) resulting common mode input voltage (v) v ia v ib v id v icm 1.25 1.15 100 1.20 1.15 1.25 -100 1.20 2.40 2.30 100 2.35 2.30 2.40 -100 2.35 0.10 0 100 0.05 0 0.10 -100 0.05 1.50 0.90 600 1.20 0.90 1.50 -600 1.20 2.40 1.80 600 2.10 1.80 2.40 -600 2.10 0.60 0 600 0.30 0 0.60 -600 0.30
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 14 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms figure 7. worst-case test pattern note: 20. the worst-case test pattern produces a maximum toggling of digital circuits, lvds i/o, and lvttl/cmos i/o. depending on the valid strobe edge of t he transmitter, the txclkin can be rising or falling edge data strobe. figure 8. transmitter lvds output load and transition times figure 9. transmitter setup/hold and high/low times (ris ing-edge strobe) figure 10. transmitter input clock transition time figure 11. transmitter outputs channel-to-channel skew
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 15 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms (continued) figure 12. receiver setup/hold and high/low times note: 21. for the receiver with falling-edge str obe, the definition of setup/hold time is slightly different from the one with rising-edge strobe. the clock reference point is the ti me when the clock falling edge passes through 2v. for hold time t rhrc , the clock reference point is the time when falling edge passes through +0.8v. figure 13. transmitter clock-in to clock-out delay (rising-edge strobe) figure 14. receiver clock- in to clock-out delay (falling-edge strobe) figure 15. receiver phase-lock-loop set time
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 16 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms (continued) figure 16. transmitter power-down delay figure 17. receiver power-down delay figure 18. 28 parallel lvttl inputs mapped to four serial lvds outputs note: 22. the information in this diagram shows the difference between clock out and the first data bit. a 2-bit cycle delay is guaranteed when the msb is out put from the transmitter. figure 19. 21 parallel lvttl inputs mapped to three serial outputs note: 23. this output date pulse pos ition works for both transmitters with 21 ttl inputs, except the lvds output bit mapping difference. two-bit cycle delay is guarant eed with the msb is output from transmitter.
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 17 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms (continued) figure 20. transmitter output pulse bit position figure 21. receiver input bit position figure 22. receiver lvds input skew margin note: 24. t rskm is the budget for the cable skew and source clo ck skew plus inter-symbol interference (isi). the minimum and maximum pulse position values are based on the bit position of each of the seven bits within the lvds data stream across pvt (pro cess, voltage supply, and temperature).
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 18 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms (continued) figure 23. transmitter clock out jitter measurement setup note: 25. test setup considers no requirem ent for separation of rms and determini stic jitter. other hardware setups, such as wavecrest boxes, can be used if no m1 software is available, but the te st methodology in figure 24 should be followed. figure 24. timing diagram of transmitter clock input with jitter note: 26. this jitter pattern is used to test the jitter respons e (clock out) of the device over the power supply range with worst jitter 3ns (cycle-to-cycle) clock input. the specific test methodology is as follows: 27. switching input data txin0 to txin20 at 0.5mhz and the input clock is shifted to left -3ns and to the right +3ns when data is high. 28. the 3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. jumping between two clock sources to simulate the worst-ca se of clock-edge jump (3ns) from graphi cal controllers. cycle-to-cycle jitter at txclkout pin should be measured cross v cc range with 100mv noise (v cc noise frequency <2mhz).
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 19 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer ac loadings and waveforms (continued) figure 25. ?16-grayscale? test pattern note: 29. the 16-grayscale test pattern tests device power cons umption for a ?typical? lcd display pattern. the test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. figure 26. transmitter phase-lock-loop time
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 20 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer physical dimensions mtd56rev3 1 623 56 51 34 28 29 0.2 c b a 0.10 ab c 0.1 c -c- 1.45 6.15 9.125 0.30 0.50 8.10 4.05 0.25 0.50 b a 7.6 figure 27. 56-lead thin shrink small out line package (tssop), jedec mo-153,6.1mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2003 fairchild semiconductor corporation www.fairchildsemi.com fin3385 / fin3386 ? rev. 1.0.6 21 fin3385 / fin3386 ? low-voltage, 28-bit flat pa nel display link serializer / deserializer

▲Up To Search▲

Price & Availability of FIN3386MTDX

	To Download FIN3386MTDX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .